PROPEL: Power and Area-Efficient Nanophotonic On-Chip Interconnect Architecture for Multicores

With technology scaling, growing wire delays and excess power dissipation of current metallic interconnects are predicted to significantly limit the performance of Networkon-Chips (NoCs) architectures. Recent research has focused on developing alternate solutions to current metallic interconnects. One potential solution is silicon photonics because of its higher bandwidth, reduced power dissipation, increased wiring simplification and its compatibility with (complementary-metal-oxide semiconductor) CMOS processing. In this paper, we propose PROPEL, a balanced power and area-efficient on-chip photonic interconnect for future multicores. PROPEL overcomes two fundamental issues facing NoCs architectures, namely power dissipation and area overhead, by a combination of multiplexing techniques (wavelength and space) and by exploiting the recent advances silicon photonics design space. Our results indicate that PROPEL is power, cost and area-efficient network when compared to the proposed on-chip optical topologies. Moreover, simulation results on synthetic traffic indicate that PROPEL outperforms both electrical and optical topologies for in-chip interconnects in terms of throughput and power.